electronics blog: FPGA VHDL 4 bit Serial to parallel shift register circuit and test bench comparison Xilinx spartan 3 Waveshare
![SOLVED: I need help creating a 4 to 1 MUX and flip flops in VHDL, to create a universal shift register. Ferialin P3:0-Parallel inputs Serialin - Serial input Q(3:0-Outputs Clock - Positive SOLVED: I need help creating a 4 to 1 MUX and flip flops in VHDL, to create a universal shift register. Ferialin P3:0-Parallel inputs Serialin - Serial input Q(3:0-Outputs Clock - Positive](https://cdn.numerade.com/ask_images/6c1621d74c884fe58de864bcee6afd94.jpg)
SOLVED: I need help creating a 4 to 1 MUX and flip flops in VHDL, to create a universal shift register. Ferialin P3:0-Parallel inputs Serialin - Serial input Q(3:0-Outputs Clock - Positive
![8.5 Registers - Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL [Book] 8.5 Registers - Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL [Book]](https://www.oreilly.com/api/v2/epubs/9780470900550/files/images/ch008-f028.jpg)